1. Field of the Invention
The present invention relates to a method of manufacturing a junction type field effect semiconductor device using a III-V Group compound semiconductor substrate.
2. Description of the Related Art
A known example of a field effect semiconductor device using a III-V Group compound semiconductor as a substrate is a GaAsFET (GaAs field effect transistor). Examples of the GaAsFET are a MES (metal semiconductor) FET and a J-FET (junction type). A so-called MES type FET using a Schottky barrier gate is widely used because its manufacturing process is simple.
Junction barrier height .PHI.B of the J-FET is as high as 1 V or more. Therefore, a sufficient operation margin can be obtained for a normally-off type J-FET. In addition, since either an N or P channel can be manufactured by selecting an impurity to be ion-implanted, a complementary circuit can be arranged.
The type of J-FET varies in accordance with a formation type of a gate region. That is, the J-FET has a variety of types such as a diffusion junction type, an ion-implantation junction type, and an epitaxial growth junction type. In any of the above types, however, it is difficult to perform micropatterning of a gate portion as compared with the MES type, and a micropatterning technique for the J-FET has not been developed yet. That is, in a conventional technique, a gate region is formed in a semiconductor substrate, and then a gate electrode is positioned on the gate region by mask alignment. Thereafter, the gate electrode is formed by a lift-off method or etching. Alternatively, the gate electrode is formed not directly on the gate region but on a region electrically connected to the gate region. In this case, the gate region is a small region. This is because mutual conductance gm as a performance factor of a semiconductor device is proportional to W (channel width)/L (channel length) and therefore W must be increased and L must be decreased in order to increase the value of gm. Since the gate region is a small region, it is very difficult for current techniques to stably position the gate electrode on the small region with high accuracy by mask alignment, resulting in a very poor yield. In addition, when the gate electrode is formed on the region electrically connected to the gate region, a gate resistance is increased by a resistance of this region. For this reason, as an operation frequency is increased, a noise factor (NF) is increased and a gain is reduced. Therefore, this method is not preferable as a method of manufacturing a gate portion of a high frequency FET.
As described above, in the method of positioning a gate electrode with respect to a gate region by mask alignment, the manufacturing yield is very poor. In the method of connecting a gate electrode with a gate region through a region connected to the gate region, a high frequency performance is degraded.